AUXSRC=clksrc_pll_sys
Clock control, can be changed on-the-fly (except for auxsrc)
| AUXSRC | Selects the auxiliary clock source, will glitch when switching 0 (clksrc_pll_sys): undefined 1 (clksrc_gpin0): undefined 2 (clksrc_gpin1): undefined 3 (clksrc_pll_usb): undefined 4 (rosc_clksrc): undefined 5 (xosc_clksrc): undefined 6 (clk_sys): undefined 7 (clk_usb): undefined 8 (clk_adc): undefined 9 (clk_rtc): undefined 10 (clk_ref): undefined |
| KILL | Asynchronously kills the clock generator |
| ENABLE | Starts and stops the clock generator cleanly |
| DC50 | Enables duty cycle correction for odd divisors |
| PHASE | This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect |
| NUDGE | An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time |